With the continued emphasis on highly integrated electronic devices, there is an ongoing need for semiconductor memory devices that operate at higher speeds and lower power and have increased device density. To accomplish this, devices with aggressive scaling and multiple-layered devices with transistor cells arranged in horizontal and vertical arrays have been under development.
Non-volatile memory devices, for example flash memory devices, are programmed as single-level cells (SLC), in that each cell stores a single bit of data. In order to increase memory size, research efforts have explored multi-level cell (MLC) programming. In MLC programming, also referred to herein as “multiple-bit”, or “multi-bit”, cell programming, two or more bits of data are stored in each cell. For example, in the case where two bits of data are stored in a memory cell, least significant bit (LSB) data and most significant bit (MSB) data are stored in each cell. In other words, in a case where a data value ‘10’ is stored in a memory cell, the MSB data is “1” and the LSB data is “0.” By adopting multi-bit programming, memory capacity can be increased without increasing memory size.
As devices continue to become reduced in size due to further integration, there is an increased likelihood of inter-cell interference during multi-bit programming, which can lead to erroneous data programming and reduced reliability.